Optical Engineer, Photonic Integrated Circuit (PIC) Design Analysis
Company: Tailored Management
Location: Redmond
Posted on: March 10, 2026
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Job Description:
Optical Engineer, Photonic Integrated Circuit (PIC) Design &
Analysis Location: Fully Onsite at Redmond, WA Duration: 12-months
with possible extension Pay Rate: $80/hr on W2 Benefits: Medical,
dental, vision; paid vacation/sick leave; 401k Job Description We
are seeking a passionate Optical Engineer to join our clients
research and development team. This role focuses on delivering
state-of-the-art near-to-eye display system technologies. The ideal
candidate will have expertise in Client integrated photonics device
design and metrology, gained through a Ph.D. or industry experience
Responsibilities Design and develop complete Photonic Integrated
Circuits (PICs), from fundamental component blocks to full-circuit
implementations, with a strong emphasis on active device
integration. Generate, verify, and prepare fabrication-ready layout
files, ensuring compliance with foundry Process Design Kits (PDKs)
for external fabrication. Conduct systematic design analysis,
including optimization and parametric studies, to guide design
decisions. Support the entire design-to-fabrication pipeline, from
initial concept through tapeout, coordinating closely with
cross-functional teams and external partners. Collaborate with
program leadership, Technical Program Managers (TPMs), and
researchers on PIC designs that align with overall program
objectives. Must HaveQualifications MS or Ph.D. degree in
Electrical Engineering, Optical Sciences, Physics, or a closely
related field. PIC Design & Simulation: 3 years designing,
simulating, and laying out photonic integrated circuits (PICs) for
visible/IR wavelengths. Photonic Modeling Tools: Proficiency with
tools like Lumerical, Ansys Photonics, Synopsys RSoft, or COMSOL
for device/circuit analysis. PIC Layout & Tapeout: Experience with
layout tools (KLayout, Cadence Virtuoso, gdsfactory), GDSII
generation, and supporting tapeouts at commercial foundries. 3
years of hands-on experience in the design, simulation, and layout
of PICs for visible or IR wavelengths on platforms such as Si, SiN,
LiNbO, or BTO. 3 years of experience utilizing photonic device
simulation and electromagnetic modeling tools for both component
and circuit-level analysis (e.g., Lumerical FDTD/MODE/DEVICE, Ansys
Photonics, Synopsys RSoft, or COMSOL Multiphysics). 2 years of
experience with PIC layout tools and GDSII generation (e.g.,
KLayout, Cadence Virtuoso, gdsfactory, or equivalent), including
familiarity with foundry PDK integration and design rule
verification. 2 years of experience with scientific programming
(e.g., Python or MATLAB) for scripting, design automation, and
analysis. 1 years of experience supporting or executing PIC
tapeouts at a commercial semiconductor foundry, including an
understanding of fabrication process constraints (e.g., propagation
losses, sidewall roughness, etch non-idealities). Preferred
Qualifications 3 years experience in active PIC design,
fabrication, and validation, particularly for visible wavelengths
on LiNbO or BTO platforms. 3 years of experience in design space
exploration, sensitivity analysis, and statistical
performance/yield modeling for photonic circuits. 3 years of
experience with one or more major photonic simulation tool suites
(e.g., Lumerical, Synopsys, COMSOL, or equivalent). 2 years of
experience utilizing photonic circuit-level simulation tools (e.g.,
Lumerical Interconnect, Synopsys OptSim, or VPIphotonics) for
system-level performance evaluation. 2 years of experience in
photonic device characterization and test, including both optical
and electro-optic measurements. 1 years experience with fiber
optics, free-space optics, PIC packaging, and comprehensive device
characterization. 1 years experience with semiconductor fabrication
processes and a deep understanding of process-induced performance
limitations, such as optical losses, sidewall roughness, and
process variability. Demonstrated ability to directly incorporate
fabrication constraints into PIC designs (e.g., optimizing minimum
feature sizes and bend radii, implementing effective tapering
strategies, and using layout techniques to mitigate scattering and
coupling losses). Pursuant to the California Fair Chance Act, Los
Angeles County Fair Chance Ordinance for Employers, Los Angeles
Fair Chance Initiative for Hiring Ordinance, and San Francisco Fair
Chance Ordinance, qualified applicants will be considered for
assignment with arrest and conviction records. Criminal history may
have a direct, adverse, and negative relationship with some of the
material job duties of this position. These include the duties and
responsibilities listed above, as well as the abilities to adhere
to company policies, exercise sound judgment, effectively manage
stress and work safely and respectfully with others, exhibit
trustworthiness, meet client expectations, standards, and
accompanying requirements, and safeguard business operations and
company reputation. TMN
Keywords: Tailored Management, Everett , Optical Engineer, Photonic Integrated Circuit (PIC) Design Analysis, Engineering , Redmond, Washington
